Synopsys Announces Design-for-Verification Methodology Built on SystemVerilog

Synopsys' Newly Renamed Discovery Verification Platform Offers Improved Quality and Productivity

"Synopsys is focused on delivering a unified platform to enable a comprehensive design-for-verification methodology," said Manoj Gandhi, senior vice president and general manager of the Verification Technology Group at Synopsys. "Such a methodology can transform our customer's verification environments by leveraging designer's intent to streamline the verification process. The combination of advanced technologies in the Discovery Verification Platform and SystemVerilog are essential to managing ever increasing verification complexity."

Synopsys' DFV methodology provides engineers with significant productivity improvements. The new approach applies streamlined specification-driven verification with assertions, concise coding practices and hierarchical chip verification techniques to ensure thorough verification of the design and to reduce the risk of functional errors that cause costly re-spins.

"At AMD, we have realized significant improvements in productivity by successfully using design-for-verification techniques like assertions -- a key feature in VCS(TM). The native assertions support in the simulator for the verification of our advanced designs is key to our requirement to tapeout clean designs," said Rich Heye, vice president and general manager of AMD's Microprocessor Business Unit. "We believe Synopsys' strong support of the Accellera SystemVerilog standard and its use of the standard to drive the design-for-verification methodology will further enhance verification productivity and quality."

"The advances in semiconductor technology combined with increased design complexity have created a need for new approaches to verify today's complex system-on-chip designs," said Shrenik Mehta, director, frontend technologies-ASICs and processors, Sun Microsystems. "A unified design and verification language, such as the Accellera SystemVerilog standard, will pave the way for the productivity and efficiency improvements needed to stay ahead of SoC challenges."

SystemVerilog enables a unified design and verification methodology that simplifies and accelerates the verification process. Providing key language components such as assertions, testbench constructs and interfaces, SystemVerilog allows new verification methodologies to be incrementally applied to existing Verilog-based flows, thus easing adoption. The use of a unified language facilitates team communication to maximize productivity.

"As users of advanced Verilog-based languages, we are impressed with SystemVerilog's powerful design features and advanced verification capabilities," said Ulrich Hummel, manager of CAD/CAE, Micronas GmbH. "With Synopsys' creation of a complete design and verification flow utilizing SystemVerilog, we expect rapid adoption of the standard throughout the industry."

Accellera SystemVerilog Support & Product Availability

The current Accellera SystemVerilog 3.0 standard is supported in VCS today on a controlled availability basis. General availability is planned for calendar Q4, 2003. Design Compiler(TM) will support SystemVerilog 3.0 for beta customers starting in Q2, 2003. Formality(R) will support SystemVerilog 3.0 for beta customers starting in Q1, 2004. The Discovery Verification Platform has been architected to support the emerging SystemVerilog 3.1 improvements. VCS and Vera(R) will support the emerging SystemVerilog 3.1 starting in 1H, 2004 for beta customers. To learn more about design for verification visit http://www.synopsys.com.

Synopsys Discovery Verification Platform

The Discovery Verification Platform is a unified environment that provides high performance and efficiency of interaction among all platform components, including mixed-HDL simulation, mixed signal, system-level verification, assertions, verification intellectual property, code coverage, functional coverage, testbenches and formal analysis. The Discovery Verification Platform includes Synopsys' VCS HDL simulator, VCS MX mixed-HDL simulator, CoCentric(R) System Studio for system-level verification, LEDA(R) programmable RTL checker, Vera testbench automation tool, Magellan hybrid RTL formal verification, DesignWare(R) verification IP, Formality equivalence checker, NanoSim(TM) and HSPICE(R) for mixed-signal simulation. Combined with SystemVerilog and Synopsys' design-for-verification methodology, the Discovery Verification Platform helps designers achieve higher levels of verification productivity by contributing to first-time silicon success within required project cycles.

About Synopsys Inc.

Synopsys, Inc. (Nasdaq:SNPS) is the world leader in electronic design automation (EDA) software for integrated circuit (IC) design. The company delivers technology-leading IC design and verification platforms to the global electronics market, enabling the development of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, Calif., and has offices in more than 60 locations throughout North America, Europe, Japan and Asia. Visit Synopsys online at http://www.synopsys.com/.

Forward Looking Statements

This press release contains forward-looking statements within the meaning of the safe harbor provisions of Section 21E of the Securities Exchange Act of 1934, including statements regarding the expected benefits of adoption of the Accellera SystemVerilog standards and the expected dates by which certain Synopsys products will support this standard. These statements are based on Synopsys' current expectations and beliefs. Actual results could differ materially from the results implied by these statements as a result of unforeseen difficulties in architecting Synopsys tools to support these standards and uncertainties attendant to any new product offering, as well other factors contained in Synopsys' Quarterly Report on Form 10-Q for the fiscal quarter ended January 31, 2003.

Note to Editors: Synopsys, Vera, LEDA, CoCentric, HSPICE, DesignWare and Formality are registered trademarks of Synopsys, Inc. VCS, Discovery, Magellan, and NanoSim are trademarks of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.

CONTACT: Synopsys, Inc.
             Carole Murchison, 650/584-4632
             carolem@synopsys.com
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             Edelman Public Relations
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